1. Technical Field
The present invention relates to method of manufacturing a semiconductor device, and in particular to a method of manufacturing a WCSP semiconductor device having a multilayer redistribution structure.
2. Related Art
In conventional integrated circuit packages of packaged semiconductor chips, such as semiconductor integrated circuits and the like, demands are increasing for size reduction and reduction in thickness. Recently, development is progressing in Chip Sized Packages (CSP's), centered around integrated circuit packages in fields with particular demands for reduced thickness. CSP's have spherical shaped external connection terminals, called bumps, disposed in a lattice on the surface of a semiconductor chip. A structural body that includes plural individual semiconductor devices formed on a semiconductor wafer by wafer processing, from which CSP's are obtained by dicing, is referred to as a WCSP (Wafer-level Chip Size Package).
Recently, multilayer redistribution structures are being introduced even in WCSP's, in order to obtain a higher degree of integration. In such multilayer redistribution structure WCSP's, in order to obtain an even higher degree of integration, a “stacked structure”, formed by via portions corresponding to each layer superimposed on an electrode pad, is proposed (Japanese Patent Application Laid-Open (JP-A) No. 2002-252310).
FIG. 45 is an example of a structure of a WCSP semiconductor of multilayer redistribution structure having a stacked structure. This semiconductor device 200 is equipped with: a semiconductor wafer 210; an electrode pad 212; a passivation film 214; a first insulation layer 216; a first opening 216a; a first Under Bump Metal (UBM) layer 218; a first redistribution layer 220; a second insulating layer 222; second openings 222a; a second UBM layer 224; a second redistribution layer 226; and a post electrode 228.
Next, a conventional method of manufacturing the WCSP semiconductor device 200 will be briefly explained, with reference to FIG. 45. First, the electrode pad 212 is formed to the surface of the semiconductor wafer 210; and the passivation film 214 is formed thereon, so as to expose the electrode pad 212 (Process 1). Next, the photosensitive first insulation layer 216 (PBO or the like) is formed on the surface of the semiconductor wafer 210, for example by spin coating, and a first opening 216a is formed by photo-exposure and development, so as to expose the electrode pad 212 (Process 2). The first opening 216a corresponds to a “first via portion”.
Next, the first UBM layer 218, of titanium (Ti) and copper (Cu), and a first resist film are deposited in sequence. The first UBM layer 218 is a layer in which a first electrically conductive material (Cu) that will later be used for the first redistribution layer 220, is deposited on a first seed layer (Ti). After patterning the first resist film with the desired redistribution pattern by photo-exposure and development, the first redistribution layer 220 is formed by growing the first electrically conductive material using electroplating. The first resist film, the first electrically conductive material at portions that have not been grown as the first redistribution layer 220, and the first seed layer are removed in sequence, completing the first redistribution layer 220 (Process 3). Note than at this stage the first redistribution layer 220 has a structure that dips inwards into the first via portion. A portion of the surface of the first redistribution layer 220 dips in further than the surface of the first insulation layer 216.
Next, after the photosensitive second insulating layer 222 (PBO or the like) has been formed on the first redistribution layer 220, the second openings 222a are formed by photo-exposure and development processing, exposing the first redistribution layer 220 at the bottom face of the first via portion. The second opening 222a corresponds to the “second via portion”. This second via portion is superimposed on the first via portion, configuring a “stacked structure 230”. Then, similar to forming the first redistribution layer 220, the second UBM layer 224, of titanium (Ti) and copper (Cu), and a second resist film, are deposited in sequence. The second UBM layer 224 is a layer in which a second electrically conductive material (Cu) that will later be used for the second redistribution layer 226, is deposited on a second seed layer (Ti).
After patterning the second resist film with the desired redistribution pattern using photo-exposure and development, the second redistribution layer 226 is formed by growing the second electrically conductive material using electroplating. When this is being performed, in order to form a stacked structure, the second resist film is patterned so as to open the region above where the first via portion and the second via portion are formed (Process 4).
Next, the second redistribution layer 226 is formed by growing the second electrically conductive material using electroplating. The second resist film, the second electrically conductive material at portions that have not been grown as the second redistribution layer 226, and the second seed layer are removed in sequence, completing the second redistribution layer 226 (Process 5). The second redistribution layer 226 has a structure that dips inwards into the second via portion. A portion of the surface of the second redistribution layer 226 dips further inward than the surface of the second insulating layer 222. Multilayer redistribution layers are similarly formed in sequence, and finally the post electrode 228, a protective film, and an external terminal are formed, obtaining the WCSP (Process 6).
However, in the conventional manufacturing method, as shown in FIG. 46, the size of the openings at each of the vertically superimposed via portions in the stacked structure 230 is extremely small. Portions also arise where the via portion of the layer above dips deeply inward at each superimposition of the first via portion and the second via portion. Due to these circumstances, as the number of via portions stacked increases, penetration of the electroplating liquid into the via portion gets more difficult.
For example, as described above (Process 5), the first redistribution layer 220 dips inward into the first via portion, and a portion of the surface of the first redistribution layer 220 dips in further than the surface of the first insulation layer 216. Consequently, a portion with deep localized dipping can arise at the second via portion superimposed on the first via portion. Therefore, when the second electrically conductive material of the second UBM layer 224 is grown, penetration of the electroplating liquid into the second via portion is difficult.
Unless the required amount of electroplating liquid is supplied to the second via portion the second electrically conductive material cannot be grown to the desired thickness. Consequently, as shown in FIG. 28, the thickness of electroplating at the via portion of the second redistribution layer 226 is locally thinner than the thickness of the electroplating at the redistribution pattern portion, and film forming defects occur between the layers, called “fault-breaks”. This results in occurrences of poor electrical connection between the second via portion and the first via portion, or, in other words, increased resistance of the stacked via.